USB Connectivity, Configuration Support Boost Effectiveness of High-Bandwidth FPGA Evaluation Board

Engineers choose field-programmable gate arrays (FPGAs) for applications such as industrial sensors and machine vision, where large amounts of data must be handled with high speed and low latency. FPGA chips, containing thousands of tiny logic blocks, can be configured in the field into digital hardware and reconfigured as requirements change. Because of their flexibility and ability to run multiple streams of logic operations simultaneously rather than sequentially, FPGAs are often preferred over microcontroller units (MCUs) and central processing units (CPUs) in high-bandwidth applications.

Lattice Semiconductor’s FPGAs connect to multiple industrial sensors or cameras, perform digital signal processing (DSP) operations, and facilitate high-speed communication. They reduce the workload on the AI processor or CPU that is next in the signal chain while maintaining a compact form factor and low power consumption.

To take full advantage of FPGA capabilities, engineers use evaluation boards to develop and test logic cell configurations that will be deployed in real-world applications. Engineers need to understand the components of development kits that include evaluation boards, the process and tools for configuring the FPGA, and how their development work will affect the application's real-world reliability.

Designing with development kits

Evaluation boards give engineers the tools they need to design and test the virtual hardware, which will be configured on the FPGA. In addition to the FPGA, an evaluation board typically has built-in flash memory, USB connections, testing and debugging connections, and connections to peripherals. Development kits add additional parts like cables and access to configuration software.

For example, the CrossLinkU-NX Evaluation Board (Figure 1) from Lattice Semiconductor contains an LIFCL-33U FPGA. It also comes with a USB-A-to-USB 2.0 micro-B cable for programming, a USB-C-to-USB-C cable for power and data transfer, and a daughter board with two peripheral module (PMOD) connectors. Using the development kit, engineers can design logic fabrics to meet the needs of their applications.

Figure 1: Lattice Semiconductor’s CrossLinkU-NX Evaluation Board features an LIFCL-33U FPGA, USB cables, and a daughter board with PMOD connections. (Image source: Lattice Semiconductor)

The 33,000 logic cells within an LIFCL-33U FPGA include sixty-four 18 x 18 multiplier blocks that can be dedicated to DSP for fast image processing. These multiplier blocks boost available bandwidth and free other logic cells for general-purpose tasks. Performance is also boosted by 3.6 Mb (equal to approximately 450 KB) of embedded memory, including embedded block RAM (EBR), large RAM (LRAM) for data buffering, and logic cells dedicated to distributed memory for local storage.

The LIFCL-33U is optimized for receiving, processing, and outputting video feeds. It is compatible with the Mobile Industry Processor Interface (MIPI) Camera Serial Interface-2 (CSI-2) Soft D-PHY, with FPGA logic cells configured as a virtual hardware interface for camera data. The FPGA also works with other protocols such as Display Serial Interface (DSI), low-voltage differential signaling (LVDS), subLVDS, and scalable low-voltage signaling (SLVS).

LIFCL-33U FPGAs are also compatible with USB protocols. The CrossLinkU-NX evaluation board (Figure 2) has two USB connectors; a micro-USB connector provides power and transmits configuration data to the FPGA, while the other also supplies power and provides a reliable connection for video output to a display, CPU, or AI accelerator.

Figure 2: A CrossLinkU-NX Evaluation Board contains an LIFCL-33U FPGA (center), SPI flash memory (above the FPGA), USB connectors (bottom left, top right), a camera connector (bottom right), and an expansion card connector (top left). (Image source: Lattice Semiconductor)

While FPGA logic cells can be configured for USB connectivity via USB 2.0 and USB 3.2 Gen 1 PHY, LIFCL-33U devices feature a hardened USB controller, a dedicated hardware block that translates and schedules output for USB connectivity. Hardened USB frees up logic cells for other processing tasks and shortens development time.

Weaving logic fabric

CrossLinkU-NX Evaluation boards include all the connectivity engineers need to quickly get started on designing the logic fabric for an LIFCL-33U FPGA. The logic fabric is the complete configuration of the FPGA’s logic cells that forms the virtual hardware the application requires. Lattice Semiconductor’s Radiant design software translates engineers’ ideas into virtual FPGA hardware. The logic fabric for LIFCL-33U FPGAs works within Lattice Semiconductor’s Nexus FPGA platform. Similar to a CPU operating system, the Nexus platform defines the FPGA routing architecture, as well as embedded memory and security features.

The first step is to define the design in a hardware description language such as Verilog or VHDL. Radiant’s synthesis process converts the description into logic gates, their states, and how they will flip based on the data received. The Radiant software is preprogrammed with the FPGA’s floor plan, a map of where the chip's major functions are located.

With the logic gate and floor-plan information, Radiant’s place-and-route step assigns each logic element to a specific location on the FPGA and ensures logic paths are properly connected. Next, the software performs a timing analysis. Timing analyses compare the time it takes a data packet to complete the designed route with the system’s required clock frequencies.

To speed the design process, Lattice Semiconductor provides reference designs that help engineers implement USB protocols. Engineers can also access pre-engineered Intellectual Property (IP) modules. IP modules are available for common tasks such as providing Ethernet connectivity or converting signals between protocols; for instance, between SPI or Inter-Integrated Circuit (I²C) protocols and USB protocols. IP modules for common DSP tasks include reorienting, resizing, or synchronizing videos or converting between video data formats.

After these steps are complete, the software generates a bitstream that defines the logic fabric of the FPGA. The bitstream is loaded into the CrossLinkU-NX evaluation board’s on-board flash memory via a USB, Joint Action Test Group (JTAG) protocol, or SPI connection. The LIFCL-33U FPGA is then configured from this flash memory.

The ability to boot directly from flash memory makes it easy for the engineer to debug and iterate the bitstream during application development. In the field, FPGA bitstreams are typically stored on external flash memory devices and copied into static random-access memory (SRAM) on system startup. SRAM allows for fast startup that initializes connectivity within 2 ms and full functionality of the custom virtual hardware within 8 ms.

Getting ready for reliability

Fast startup with SRAM is one of the advantages of using FPGAs for applications like sensor signal or video processing that require high bandwidth. LIFCL-33U FPGAs also use up to 75% less power than similar FPGAs. Manufactured with reliable 28 nm technology, LIFCL-33U devices are built with Fully Depleted Silicon-On-Insulator (FD-SOI) construction that reduces unwanted leakage currents and electrical noise, improves radiation tolerance, and performs well at low voltages. LIFCL-33U devices operate at voltages between 1.0 and 1.8 V in high performance (HP) mode for data rates up to 1.2 Gbps per lane, and between 1.2 and 3.3 V in wide range (WR) mode for slower data rates.

Power consumption is a particular concern with embedded and mobile applications that rely on battery power or continuously operate on standby. LIFCL-33U FPGAs have an Always-On mode with a low-power standby, enabling the system to wait for a triggering input while conserving power.

Another set of LIFCL-33U features helps engineers design robust, high-uptime applications for industrial settings by enhancing security with bitstream encryption and password protection. The FD-SOI construction reduces vulnerability to bit-flip errors caused by cosmic radiation and other electromagnetic disturbances. Should an error occur, it can be detected and repaired by the FPGA’s soft error detection (SED) / soft error correction (SEC) capability.

Conclusion

Evaluation boards such as Lattice Semiconductor’s CrossLinkU-NX allow engineers to access the flexibility, reliability, efficiency, and low-latency, high-bandwidth processing power of LIFCL-33U FPGAs. Their built-in USB, SPI, MIPI, and JTAG connectivity, along with Lattice Semiconductor’s Radiant programming software, enables rapid video and sensor application development, while evaluation boards let engineers quickly reconfigure FPGAs for changing peripherals or requirements without the need to change physical hardware.