Amazing has adopted a unique design when developing TVS array products for high-speed interfaces. In addition to having a dual-channel package design (top left) to ensure better jitter characteristics, in the cross parasitic capacitance part between I/O 1 and I/O 2 (top right), processes such as Deep Trench, Deep Nwell, or N Buried Layer will also be used to block the formation of parasitic BJT elements. This is used to reduce the formation of its parasitic capacitance. In comparison with competitors, it can be found that the cross capacitance of Amazing AZ1023-02F can be as low as 0.04 pF. The cross capacitance of the competitor's product in the same package is 0.3 pF. It is obvious that Amazing’s TVS has the advantages of low capacitance design.