The differentiating features of the LX2160A are shown in this block diagram. The LX2160A uses 16 Arm^® Cortex-A72 running at 2.2GHz with 64-bit DDR controller, 1MB of L2 cache per cluster (8MB total) and 8MB of L3 cache. The L3 cache is sized such that for demanding workloads, packets normally are resident in the cache by the time that the cores want to inspect the content. This reduces latency and pressure on the DDR bandwidth. Also worth noting are the Network interfaces with 100G, 50G, 40G, 25G, 10G, 2.5G, and 1G Ethernet MACs and a hardware L2 switch. Along with the Ethernet controllers, the LX2160A has 24 lanes of SerDes for high performance PCIe Gen4, with virtualization support, and SATA3.0. The SoC also has the DPAA2 with up to 100 Gbps of data compression and decompression and 50 Gbps security.